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hot_img Samsung Electronics plans to repurpose the NRD-K R&D production line for wafer foundry use, aiming for mass production of 2nm base chips for HBM

According to South Korean media ZDNet Korea, Samsung Electronics is adjusting the original purpose of its NRD-K Line 2 at the Giheung campus from a research and development facility to a wafer foundry line, with the main target product being the 2nm base chips required for NVIDIA's HBM. This production line is expected to be operational in the second half of 2028, adopting a "Send-Fab" model, which involves receiving wafers from other mass production lines and performing specific processes.NRD-K is the most advanced composite research and development campus built by Samsung Electronics to seize future semiconductor technology, with a total investment of approximately 20 trillion won, planning for three production lines, of which the first line is scheduled to be completed by the end of 2024. This adjustment aims to proactively respond to the expansion of HBM demand driven by investments in AI infrastructure. Samsung plans to first apply the 2nm process to custom HBM and HBM5 to maintain performance advantages.Industry insiders point out that the scale of NRD-K Line 2 is relatively small, making it suitable for operation in the Send-Fab format. However, there are still about two years until the production line is operational, and the final purpose may be adjusted again based on market conditions. Samsung had previously considered using this production line for DRAM production, but after modifications to the relevant plans this month, DRAM capacity will be more concentrated in the Pyeongtaek campus. Equipment procurement orders have not yet been officially issued.

Data: The high-position chips of BTC in 2025 have decreased by 41.5%, and the market's maximum supply pressure may be easing

On-chain analyst Murphy stated that currently, all chips bought in BTC in 2025 are basically in a state of loss. Therefore, apart from wallet migrations, the reduction in the scale of 2025 chips likely means that holders are cutting losses and selling. Data shows that as of now, approximately 4.77 million BTC chips bought in 2025 remain, a decrease of 41.5% from the peak in December last year.From the downward trend, this group has experienced two phases: a rapid decrease in chips before February this year, and a significant slowdown in the rate of decline after February, although it still maintains a certain slope. Murphy believes that the 2025 chips may be the largest potential supply side in the current market scale. In contrast, the BTC chips formed in 2024, 2023, and 2022 have basically completed the release of high-level locked positions due to still having unrealized gains, and the slope of the curve is gradually flattening, indicating that the selling pressure from long-term holders is weakening.Historical data shows that during the bottom phases of the past two bear markets, high-level chips have shown a significant decline: at the bottom of the bear market in 2022, the chips bought at high levels in 2021 decreased by about 51%; at the bottom of the bear market in 2018, the chips bought at high levels in 2017 decreased by about 62%. If we refer to historical cycles, Murphy believes that in this bear market bottom phase, the reduction of high-level chips in 2025 may be in the range of 50%-60%, and the current decline of 41.5% indicates that there is still some room for release. However, this judgment has not yet considered the BTC bought by institutional investors such as spot ETFs and MicroStrategy, as this portion of chips is mostly in a long-term locked state, which may reduce the actual market supply pressure.

hot_img Samsung Electronics' LSI division introduces Anthropic Claude, significantly shortening the chip design and verification cycle

According to ChosunBiz, Samsung Electronics' System LSI Division has introduced Anthropic's AI programming tool Claude Code for semiconductor design and verification work, with some task cycles shortened to less than one-tenth of the original time. In the verification of data connection structures for customer-customized SoCs, work that was originally expected to take over a month was completed in two days; an engineer with two years of experience completed USB device model development and Android driver adaptation in one day using Claude Code, whereas similar work typically required a month.Samsung opened Claude Code to software developers in May this year and later expanded it to the semiconductor professional development field. The System LSI Division has about 6,000 employees, while its main competitor Qualcomm has about 52,000 employees. Samsung is trying to bridge the manpower gap with AI tools. Meanwhile, Samsung's DS Division is promoting an "AI transformation," extending generative AI from research and development to the entire business process, including production, marketing, and support. The report also pointed out that Claude has exhibited behavior in some verification tasks where it disguised erroneous information as ordinary messages or modified design code without authorization. Samsung emphasized the need for strict control and manual review of the scope and results of AI tasks.

hot_img SK Hynix: The competition in AI data centers is shifting from single chips to overall infrastructure architecture

SK Hynix stated in a recent article that the competition in AI is shifting from the performance of individual chips to the design and operation of the entire infrastructure architecture. The competitiveness of AI data centers no longer depends on individual components, but on whether the five key elements of computing, memory, storage, networking, and power cooling can be seamlessly integrated.The article points out that the continuous expansion of AI model scales has led to a surge in demand for computing power and data movement. Training requires repeatedly reading massive datasets, while inference relies on quickly retrieving user request information, both of which place higher demands on the system architecture of data centers. At the memory level, HBM, server DRAM, and others have formed a hierarchical system, each undertaking different bandwidth and capacity tasks. At the networking level, as large-scale training and inference rely on multi-server parallel processing, networking has become a key factor determining the scalability of data centers. System design is shifting from single-server to whole rack and cluster-level expansion.According to Omdia's forecast, the AI data center chip market will grow from $123 billion in 2024 to $207 billion in 2025, reaching $286 billion by 2030. SK Hynix also mentioned that Microsoft's Fairwater data center in Wisconsin is about the length of five football fields, indicating that infrastructure is being deployed on a larger scale. SK Hynix emphasizes that memory is becoming a key layer connecting computing and data.
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