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first_img Samsung Electronics accelerates the construction of the first mass production line in Pyeongtaek P5, with the equipment introduction target moved up to the second quarter of next year

According to a report by ZDNet Korea on September 28, Samsung Electronics is accelerating the construction of the first mass production line (Ph1) at the Pyeongtaek Fifth Campus (P5) and is discussing with major equipment manufacturers to move the target for Ph1 equipment installation from the originally planned third quarter of next year to the second quarter of next year. P5 is the next-generation semiconductor production base aimed to be operational by 2028, and the construction of the Ph1 cleanroom began in the third quarter of this year.Samsung Electronics had previously advanced the completion of the P5 Ph1 cleanroom, originally scheduled for early next year, by about six months, so the equipment installation is expected around the third quarter of next year. Industry insiders say that the start time for equipment installation is planned to be moved up from July to August next year to around May to June next year; others have indicated that Samsung has even proposed to deliver equipment in the first quarter of next year for temporary storage at other locations, showing a strong willingness to invest early.Discussions on the investment for the second phase of P5 (Ph2) are also progressing. Currently, Ph1 is more likely to be built as a DRAM and HBM production line, while Ph2 is more likely to be built as an advanced NAND production line, including the tenth generation (V10). Equipment industry insiders say that formal purchase orders have not yet been placed, but Samsung has discussed building Ph2 as a NAND production line with partners, and due to the long equipment delivery cycle, they are requesting to prepare relevant components in advance. Reports indicate that large global tech companies are increasing orders for high-performance DRAM and NAND for AI infrastructure, while storage companies like Samsung have limited production capacity. Samsung stated during the second quarter earnings call in July that unmet demand this year will extend into next year, and the supply shortage next year will be more severe than this year, with shortages expected to continue until 2028.

first_img Analysis: 1b DRAM unit area value exceeds TSMC 2 nanometers

Semiconductor analysis firm Kernel Insight: Demand for artificial intelligence drives DRAM prices to maintain historical highs, with the unit area sales value of the latest process DRAM exceeding the wafer prices of TSMC's N2 and N3. The firm estimates TSMC's 300mm N3 wafer price at $20,000 and N2 at $30,000, translating to nominal prices of approximately $0.283 per square millimeter and $0.424 per square millimeter, respectively, not accounting for edge losses, cutting losses, yield, and defects.Based on a price of $1.50 per Gb and generational bit density calculations, 1y DRAM is $0.329 per square millimeter, 1z is $0.410 per square millimeter, and 1b is $0.654 per square millimeter, more than 50% higher than N2. The 10nm process gradually shrinks in the order of 1y, 1z, 1a, and 1b. The above prices per Gb assume they are close to spot prices; DRAMeXchange data shows that on September 21, the average transaction price for 16Gb DDR5 eTT chips was $24.80, approximately $1.55 per Gb.There are differences in comparison metrics. TSMC's figures represent the wafer foundry prices paid by customers, while the DRAM figures represent the total sales potential of finished products and do not include advanced packaging costs; TSMC's actual supply prices will vary with order volumes and contracts. DRAM metrics are based on small spot prices, differing from the long-term contract prices of Samsung Electronics, SK Hynix, and Micron's revenue entities. Recently, non-public fixed trading prices have strengthened; if they have not yet fully reflected in spot prices, the leading margin of wafer unit prices for memory manufacturers may be even greater.

first_img Samsung Electronics adjusts the next-generation DRAM roadmap, naming B1b as D0a

According to a report by ZDNet Korea, Samsung Electronics is adjusting its next-generation DRAM strategy by incorporating the previously project-based B1b into its official roadmap, naming it the first DRAM D0a below 10 nanometers. Previously, D0a referred to vertical transistor DRAM, and this product is now classified separately as D0a-V. This renaming aims to accelerate the introduction of advanced packaging in general DRAM.B1b will manufacture storage cells and peripheral driver circuits on different wafers before bonding them together, using wafer-to-wafer hybrid bonding and directly connecting through copper interconnects. The currently commercialized DRAM is 1c, which is the 6th generation 10 nanometer level, with a line width of about 11 to 12 nanometers; the next generation 1d is the 7th generation 10 nanometer level, with a line width of about 10 to 11 nanometers, considered effectively the last 10 nanometer level product, with the related line width being a marketing term rather than an actual physical size. Vertical transistors can arrange transistors within the cell vertically, reducing the cell area from 6F² to 4F², but they need to address high aspect ratio etching and leakage current, making development more challenging. Wafer-to-wafer hybrid bonding has already been mass-produced in CMOS image sensors and high-stacking NAND.Samsung Electronics is evaluating the use of B1b for the 8th generation high bandwidth memory HBM5. HBM5 is expected to be mass-produced around 2029, aiming to increase operating speed by more than 50% compared to HBM4E. Industry estimates suggest that D0a DRAM based on B1b will be commercially available in about two years, with specific mass production investment schedules likely to be determined by mid-next year.

first_img Samsung Electronics and SK Hynix raise third-quarter operating profit expectations

According to the Chosun Ilbo report on September 15, Samsung Electronics and SK Hynix's third-quarter operating profit consensus has been raised again within three months. Based on reports from major brokerages and overseas investment banks, Samsung Electronics' estimated operating profit for the third quarter is approximately 114 trillion won, an increase of 12.2836 trillion won (12%) from 101.9052 trillion won three months ago, and a 28% increase from 89.4 trillion won in the second quarter. SK Hynix's estimate for the third quarter is 78.8035 trillion won, a 4% increase from 75.7249 trillion won three months ago, and a 30% increase from 60.5426 trillion won in the second quarter.TrendForce expects the fixed transaction prices for general DRAM in the third quarter to rise by 13% to 18% quarter-on-quarter, while NAND flash is expected to rise by 10% to 15%. The securities industry is paying attention to Samsung Electronics' HBM4 revenue share, which expanded from 5% in the first quarter to about 35% in the second quarter, along with improvements in yield rates. SK Hynix maintains the largest market share in HBM, but improvements in Samsung's HBM4 mass production may dilute its supply premium. Citigroup Securities has lowered SK Hynix's third-quarter operating profit estimate from 76.7 trillion won to 74 trillion won due to the strengthening of the won. Micron will announce its fourth-quarter results for fiscal year 2026 (June to August) on the 30th, with revenue guidance of $49 billion to $51 billion.

first_img CXMT has launched the equipment bidding for the new factory in Shanghai and is planning to expand production in multiple locations

China's largest DRAM manufacturer Changxin Storage (CXMT) has recently launched a bidding for equipment from partners for its new factory in Shanghai and is advancing capacity expansion in multiple locations. CXMT is currently mass-producing DRAM in Hefei Phase II and Beijing Phase I, with an estimated capacity of about 200,000 wafers per month, which may exceed 300,000 wafers per month by the end of the year.CXMT plans to open the new factory in Shanghai in the fourth quarter of this year, and the related equipment bidding has already started. Semiconductor equipment industry insiders say that the factory is planned to be expanded in two phases, with capacity significantly exceeding 100,000 wafers per month. Subsequently, there are plans to open a new factory in Hefei in the first half of next year and the earliest new factory in Beijing in the second half of next year, with another new factory in Hefei opening in the first half of the year after next.Equipment industry insiders say that CXMT has communicated with multiple parties regarding the timing of building factories in various locations. If all plans are realized, CXMT could add at least 70,000 to 80,000 wafers of capacity per month each year from this year until 2028, with a long-term goal of exceeding 600,000 wafers per month. Samsung Electronics and SK Hynix's DRAM capacities are estimated at about 700,000 wafers and 600,000 wafers per month, respectively.

first_img SK Hynix stated that 3D DRAM development can utilize foundry processes

SK Hynix stated on the 9th that the development of the next-generation memory 3D DRAM semiconductor can utilize foundry processes. The day before, at the 2026 SK Hynix Future Forum held at the Supex Center in the Icheon campus, Vice President Kim Kyung-hoon and Son Ho-young presented the main technical directions for 3D DRAM, including the use of logic foundry processes for DRAM peripheral circuits, maximizing data bus bandwidth, and ultra-short distance transmission.3D DRAM is the next-generation DRAM that vertically stacks the originally planar storage cells to improve integration. The two stated that achieving this technology requires addressing not only design and heat dissipation issues but also challenges in fine interconnections, bonding, and process integration in the packaging field. As the boundaries between front-end and back-end packaging, foundry, and memory technology converge, collaborative optimization beyond existing fields will become more important. Son Ho-young mentioned that 3D technology is changing the technological boundaries between wafer fabs and packaging, and it is necessary to establish an optimization and new collaboration system that transcends existing fields alongside innovations in advanced packaging technology.In a related presentation, Professor Shin Chang-hwan from Korea University stated that 3D DRAM is not only about the vertical stacking of chips but also a technology that breaks the boundaries between memory and logic. As device miniaturization approaches its limits and the time and power consumption associated with data movement between systems and memory increases, the shift to 3D technology is inevitable. He proposed a 3D integrated design framework that links materials, devices, packaging, and architecture through artificial intelligence. SK Hynix President Kwon Oh-joon, in his speech, remarked that the past memory market resembled a straight road where the competition was about who could run faster, but now it resembles a constantly changing curve, making it important to grasp the speed and direction of external environmental changes and adapt flexibly in addition to internal capabilities.

first_img Korean brokerage warns that Samsung and SK Hynix have less than 10 days of memory inventory

KB Securities warned that the inventory of memory semiconductors at Samsung Electronics and SK Hynix has fallen to less than 10 days of supply, and the available supply next year will be significantly insufficient. The agency reported on Monday that investment in artificial intelligence infrastructure is expanding at an unprecedented pace, leading to a severe supply shortage in the memory chip market. A key factor is the transition to HBM4, which requires about three times the wafers of traditional DRAM, and limited wafer capacity will reduce the available capacity of traditional DRAM.KB Securities expects that next year, the demand for DRAM and NAND will exceed supply by more than 10 percentage points. Research director Kim Dong-won stated that artificial intelligence servers will consume HBM, server DDR5, and enterprise-grade solid-state drives, potentially leading to a historic shortage. Global hyperscale data center operators have raised their expectations for artificial intelligence infrastructure investment next year to $1.3 trillion, a 60% increase from the previous year. The agency anticipates that memory semiconductors will account for 57% of total investment in artificial intelligence infrastructure next year, up from 14% last year, with TrendForce estimating this ratio could reach as high as 68%. Samsung Electronics' stock price has dropped nearly 28% from its peak, while SK Hynix has fallen nearly 40%.

first_img SK Hynix accelerates the expansion of its 1c DRAM market share, becoming the main force by early next year

According to the Chosun Ilbo report on September 7, SK Hynix is accelerating the increase of the production share of 10-nanometer sixth-generation (1c) DRAM. Industry data shows that its 1c DRAM share rose from about 10% in the first quarter of this year to about 13% in the second quarter, and is expected to reach about 24% in the third quarter and about 34% in the fourth quarter; it may rise to about 35% in the first quarter of next year, surpassing 1b (about 33%) for the first time and becoming the main process. The share of 1b (10-nanometer fifth-generation) DRAM peaked at about 43% in the second quarter of this year and has since begun to decline.By the end of the second quarter, Samsung Electronics had a 1c share of about 16% and Micron about 19%, both higher than SK Hynix's approximately 13%. Reports indicate that SK Hynix is accelerating the transition in the second half of the year, and in the fourth quarter, it may exceed Samsung Electronics' approximately 31% with about 34%. SK Hynix stated in its second-quarter earnings call that the supply of DRAM using the 1c process will substantially begin from the second quarter, and in the second half of the year, with the ramp-up of HBM4 and increased shipments of 1c general DRAM, the bit growth rate will be higher than in the first half.Samsung Electronics will use 1c DRAM starting with HBM4, with a running speed of about 11.7Gbps; SK Hynix previously prioritized ensuring mass production stability with verified 1b DRAM and advanced MR-MUF packaging, and will use 1c DRAM for the first time as the core chip for HBM starting with the next generation HBM4E. Counterpoint Research and others estimate that this year, the market share of HBM4 under the combined metrics of Nvidia, Google, and AMD is approximately 50% for SK Hynix in the mid-range, 20% for Samsung Electronics in the later range, and 10% for Micron in the later range.
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