tsmc

Taiwan Semiconductor Manufacturing Company (TSMC) has fully started production at its first wafer fab in Singapore, driven by demand for AI infrastructure.The factory is a joint venture with NXP and began trial production in June, achieving a yield rate of 99%. Mass production is planned for early 2027. TSMC holds approximately 19% of the shares.

According to the Economic Daily, major companies such as Apple, NVIDIA, AMD, Qualcomm, and MediaTek are racing towards AI and high-performance computing, recently increasing their orders for TSMC's 2-nanometer family capacity by 10% to 20%. As a result, TSMC is accelerating the expansion of its 2-nanometer family, with progress exceeding expectations. TSMC has consistently refrained from commenting on customer information and market rumors.The market originally estimated that TSMC's monthly capacity for the 2-nanometer family would be around 90,000 to 100,000 wafers by the end of this year, with expectations for continued double-digit growth to reach 110,000 to 140,000 wafers by 2027. Industry sources indicate that due to strong customer demand, the monthly capacity is expected to surge to 120,000 wafers by the end of this year, achieving the originally set 2027 target ahead of schedule. Sources say that in response to the demands from Apple and non-Apple customers, the speed and scale of new capacity for the 2-nanometer family are setting new records, far exceeding the ramp-up speed of the 3-nanometer family in its first year.TSMC's Senior Vice President and Co-COO, Wei Chen-Hao, stated at this year's North America Technology Forum that in response to strong demand from AI and other sectors, there will be five 2-nanometer fabs ramping up simultaneously for the first time this year, including two in Hsinchu and three in Kaohsiung; the wafer output in the first year of 2-nanometer will increase by 45% compared to the first year of 3-nanometer in 2023; the compound annual growth rate of 2-nanometer capacity from 2026 to 2028 will reach 70%. TSMC's 3-nanometer capacity in the Southern Taiwan Science Park is expected to reach nearly 180,000 wafers per month in the fourth quarter of this year, and three new 3-nanometer fabs are being established in Taiwan, Arizona in the United States, and Japan. The second fab in the United States is planned to begin mass production in the second half of 2027.

Semiconductor analysis firm Kernel Insight: Demand for artificial intelligence drives DRAM prices to maintain historical highs, with the unit area sales value of the latest process DRAM exceeding the wafer prices of TSMC's N2 and N3. The firm estimates TSMC's 300mm N3 wafer price at $20,000 and N2 at $30,000, translating to nominal prices of approximately $0.283 per square millimeter and $0.424 per square millimeter, respectively, not accounting for edge losses, cutting losses, yield, and defects.Based on a price of $1.50 per Gb and generational bit density calculations, 1y DRAM is $0.329 per square millimeter, 1z is $0.410 per square millimeter, and 1b is $0.654 per square millimeter, more than 50% higher than N2. The 10nm process gradually shrinks in the order of 1y, 1z, 1a, and 1b. The above prices per Gb assume they are close to spot prices; DRAMeXchange data shows that on September 21, the average transaction price for 16Gb DDR5 eTT chips was $24.80, approximately $1.55 per Gb.There are differences in comparison metrics. TSMC's figures represent the wafer foundry prices paid by customers, while the DRAM figures represent the total sales potential of finished products and do not include advanced packaging costs; TSMC's actual supply prices will vary with order volumes and contracts. DRAM metrics are based on small spot prices, differing from the long-term contract prices of Samsung Electronics, SK Hynix, and Micron's revenue entities. Recently, non-public fixed trading prices have strengthened; if they have not yet fully reflected in spot prices, the leading margin of wafer unit prices for memory manufacturers may be even greater.

Supply chain sources say that TSMC's wafer foundry prices are set to rise again, with adjustments to Wafer Out prices based on different processes starting from January 2027, with an increase of about 3% to 6%. The utilization rate of 8-inch factories exceeds 100%, and processes below 45 nanometers are fully loaded, with order visibility extending to 2030. The increase for advanced processes is higher, while mature and specialty processes are negotiated individually based on products, utilization rates, and customer conditions. TSMC has not responded to market rumors.Supply chain sources indicate that TSMC's 2-nanometer and 3-nanometer processes are in short supply, and the pressure on advanced packaging capacities such as CoWoS has not been alleviated. Customers find it difficult to switch suppliers immediately even in the face of price increases. The factory in Arizona, USA, reflects higher manufacturing costs, and the foundry quotes remain high. After the price adjustment, quotes from foundries such as Samsung Electronics, Intel, United Microelectronics Corporation, and World Advanced, as well as testing and packaging factories and IC design customers, may also be affected. United Microelectronics Corporation, Powerchip Semiconductor Manufacturing Corporation, and World Advanced have announced price increase strategies, which will continue until 2027.The supply chain states that this wave of AI demand has increased the need for PMIC, MCU, driver ICs, analog ICs, and sensors, in addition to GPUs, ASICs, and HBM. IC design companies point out that after the wafer price increase, product costs need to be reassessed, with higher-end GPUs and ASICs having relatively larger pass-through space. TSMC Chairman Wei Zhejia has stated that customers do not switch wafer foundry partners just because they are dissatisfied today. Supply chain sources say that orders transferred from Google, Apple, NVIDIA, and others mostly involve non-core chips or limited-scale orders, with no significant changes observed in the high-end process customers' chip placements.

TSMC's 2-nanometer N2 mass production marks the transition of advanced semiconductor processes from FinFET to GAA generation. Industry analysts point out that with the simultaneous increase in process complexity, CMP track counts, wafer monitoring frequency, and material specifications, the demand for equipment, CMP consumables, reclaimed wafers, and advanced materials is rising, providing growth opportunities for suppliers like Zhongsha, Shengyang Semiconductor, Xinying Materials, and Songsheng. TSMC's N2 adopts nanosheet GAA technology, which can improve performance by 10% to 15% at the same power consumption compared to N3E, or reduce power consumption by 25% to 30% at the same speed, with chip density increasing by over 15%.In Zhongsha's largest customer Diamond Disk business, advanced processes account for 63%, with N3 and N2 each accounting for 22%, and 1.4 nanometers already shipped in small quantities; after N3 enters N2, the value of CMP content increases by 10% to 15%. Shengyang Semiconductor's monthly production capacity for reclaimed wafers is adjusted to 1.1 to 1.2 million pieces by the end of 2026, with a capital expenditure budget of 4.82 billion yuan for 2026, and it is estimated that the compound annual growth rate for reclaimed wafer expansion from 2025 to 2029 will reach 25% to 30%. Xinying Materials' core products Rinse, BARC, and EBR are expected to see shipments rise seasonally as N2 capacity ramps up, while Songsheng's semiconductor revenue accounted for 66% in the first half of the year, with a year-on-year increase of about 25%, and TSMC-related revenue increased by about 170% year-on-year.

According to the Industrial and Commercial Times, TSMC is advancing the 1.4 nanometer (A14) advanced process and accelerating the construction of the Central Science Park's fourth factory. As of early September 2026, the construction progress of the Central Science Park Phase II P1 factory is smooth, with completion expected in April 2027, followed by equipment installation and trial production; the P2 factory is being advanced simultaneously, with completion expected by the end of 2027 for equipment adjustment with the P1 factory and readiness for mass production.The report states that all four 1.4 nanometer wafer fabs in the Central Science Park are expected to be completed and enter large-scale mass production by the second quarter of 2028. Major customers for A14 include Apple, NVIDIA, AMD, Qualcomm, MediaTek, Broadcom, and cloud service providers, with an estimated monthly capacity of 120,000 to 160,000 12-inch wafers, contributing an estimated annual revenue of $45 billion to $52 billion for TSMC.

As we enter the late third quarter of 2026, TSMC's 3nm and 2nm advanced process and CoWoS advanced packaging capacity continue to be in high demand. NVIDIA and Apple continue to dominate the resources for advanced processes and packaging; Amazon AWS's Annapurna has recently increased its AI self-developed chip production, securing more 3nm capacity. MediaTek, in addition to mobile chips, is also competing for 2/3nm process and CoWoS-S/L capacity with large orders related to Google TPU.There are reports that TSMC has recently readjusted its capacity allocation. After MediaTek secured a large order from Google TPU, the next-generation TPU v9 will simultaneously use TSMC's CoWoS-L and Intel's EMIB-T, which has slightly adjusted MediaTek's 3nm and 2nm capacity arrangements. Currently, TSMC's main customer for 3nm is NVIDIA, which is expected to surpass Apple to become the largest customer by 2025; the demand for 2nm is primarily from Apple and others. After AWS increased Annapurna's production, its 3nm and CoWoS configuration priority has improved.Starting in early 2026, TSMC will accelerate capacity expansion, with the 2nm monthly capacity of Hsinchu Baoshan Fab 20 and Kaohsiung Fab 22 reaching 50,000 wafers each by the end of October, totaling about 100,000 wafers; by the end of October, the monthly capacity for 3nm in Tainan Science Park is about 185,000 wafers. As of the end of September, the overall capacity utilization rate is about 96.2%, with 100% utilization for processes below 16/12nm down to 2nm. The shortage of CoWoS supply has driven advanced packaging orders to overflow, with the priority for orders going to ASE Group's Siliconware Precision Industries first, followed by Amkor, and Chipbond, among others. Chipbond's related testing and packaging capacity is fully loaded, with order visibility extending to 2028.

According to Taiwan's "Commercial Times" report on September 14, as the computing power of GPUs and ASICs continues to rise, traditional copper interconnects are gradually approaching the limits of power consumption and signal transmission. TSMC is accelerating its layout for co-packaged optics (CPO). The industry is optimistic that if CPO bandwidth continues to double every two years, it may form the "CPO Moore's Law" of the AI era. Industry analysis indicates that the upgrade of CPO bandwidth mainly has three paths: including increasing single-channel speed from 200G to over 400G, expanding the number of optical channels from 16 to 32, 64 or more, and introducing wavelength division multiplexing (WDM). By 2040, the theoretical value could reach about 128 times the current level, with long-term potential for development towards hundreds of T based on the current level of about 3.2T.TSMC's role in optical interconnects has extended from wafer foundry to system integration, gradually integrating computing, HBM memory, and high-speed I/O from 3DFabric, CoWoS, SoIC to silicon photonics and CPO. When high-speed electrical signals exceed 200G, signal attenuation increases after passing through longer copper paths such as ABF substrates, PCBs, and connectors, leading the industry to develop shorter copper paths and longer optical paths. In terms of packaging architecture, the optical engine is currently laid out on the substrate, and the next step is expected to place CPO in the intermediary layer, with future possibilities of using SoIC technology to achieve 3D vertical integration of photonic integrated circuits (PIC) and ASICs. Industry players indicate that CPO still needs to overcome challenges in packaging, optical coupling, and testing before mass production can be achieved.

The supply chain reveals that TSMC has disclosed its expansion targets for 2/3 nanometers for the first time next year. The 2-nanometer production is expected to increase from 90,000 wafers at the end of this year to 110,000 wafers by mid-next year, an increase of 22%; the 3-nanometer production is expected to rise from over 180,000 wafers at the end of this year to 210,000 wafers by mid-next year, an increase of over 16%. TSMC did not comment on market rumors yesterday and emphasized that capacity-related statements are based on the company's announcements.It is reported that TSMC's monthly capacity for 3 nanometers reached 120,000 to 130,000 wafers at the end of last year and is expected to expand to 180,000 wafers by the end of this year, with a target of over 210,000 wafers by mid-next year. The monthly capacity for 2 nanometers is expected to reach 90,000 wafers by the end of this year. TSMC previously stated that capital expenditures in 2026 will range from $60 billion to $64 billion, with approximately 70% to 80% allocated for advanced processes, and plans to add three 3-nanometer fabs located in Taiwan, Arizona in the United States, and Japan, while converting 5-nanometer equipment in Taiwan to support 3-nanometer capacity.

TSMC announced the latest monthly data, with revenue in August reaching 514.8 billion New Taiwan Dollars, a year-on-year increase of 53.3%.From January to August 2026, TSMC's consolidated revenue was approximately 3 trillion 386.87 billion New Taiwan Dollars, an increase of 39.3% compared to about 2 trillion 432 billion New Taiwan Dollars in the same period of 2025. In absolute terms, revenue in the first eight months increased by over 95 billion New Taiwan Dollars compared to the same period last year.

The Central Science Management Bureau confirmed on the 9th that TSMC's Central Science Phase II 1.4 nanometer factory expansion is fully accelerating. The first P1 factory has completed its steel structure and is expected to begin trial production in April next year, with mass production anticipated in the second half of next year, ahead of the originally scheduled mass production in 2028. TSMC has applied to the Central Science Management Bureau to set up two temporary offices at the site, which are expected to be completed in April next year, with the first batch of over 5,400 operational and outsourced personnel moving in.The advanced process new factory for TSMC's Central Science Phase II park broke ground last October, planning to build four 1.4 nanometer factories, with nearly 2,000 workers working day and night. The P1 factory is currently undergoing floor and exterior wall construction, with the factory building expected to be completed early next year. The P2 factory has begun basic construction and is scheduled to be completed in October next year, with both factories expected to start mass production successively next year. The P3 factory has obtained a construction permit, while the P4 factory is in the process of applying for a construction permit, planning to be built with a six-month gap. P3 is expected to be completed in the second quarter of 2028, and P4 is scheduled for completion in the fourth quarter of the same year. After the P2 factory is completed in the second half of next year, an additional 1,000 operational personnel will be added, with the total number of employees expected to be between 9,000 and 10,000 when all four new factories in Phase II are completed and put into production.

The supply chain reports that the capacity for high-end testing interfaces for AI chips is tight. NVIDIA has significantly raised prices to secure the capacity of mainstream testing interface vendors' probe cards and test sockets, causing some R&D and engineering validation demands to be squeezed out.Including wafer foundry TSMC and chip manufacturers, multiple supplier validations have been initiated to cope with the supply pressure after capacity has been locked.

On September 8, TSMC announced that starting in 2030, it will adopt a new "high NA" extreme ultraviolet (EUV) lithography machine manufactured by ASML from the Netherlands for mass production. Both parties also stated that they will carry out industry-wide improvements on the high NA machines. ASML monopolizes the supply of EUV lithography machines used to form nanoscale ultra-fine circuits and will begin shipping high NA machines capable of drawing finer circuits starting in December 2023. Intel has already introduced high NA machines, while TSMC previously delayed mass production due to high costs and other reasons.TSMC and ASML will launch an industry-wide project to enlarge the photomask, which serves as the original circuit pattern, from the current 6-inch (approximately 15 centimeters) square to a 12-inch square, and develop high NA machines and related components corresponding to the large masks. A large mask pilot production line is planned to be established before 2031, and the high NA machines corresponding to the large masks are expected to reach a state suitable for advanced semiconductor production before 2033. Major semiconductor manufacturers and mask companies have expressed interest in participating.High NA machines can draw finer circuits, but the area that can be drawn in a single exposure is reduced to half that of traditional models, requiring multiple exposures for large chip circuits, which complicates the process and increases costs. Enlarging the photomask can expand the exposure area and reduce costs. TSMC Chairman and CEO C. C. Wei stated that the company will gather expertise from the entire industry to continuously promote technological innovation that makes advanced technology widely usable and convey its benefits.

Taiwan Semiconductor Manufacturing Company, Micron, and other companies are increasing capital expenditures to expand production, driving the combined orders of the top five semiconductor engineering firms—HanTang, Axiom, FanXuan, Yankee, and ShengHui—to exceed 880 billion yuan, a record high. Taiwan Semiconductor Manufacturing Company recently stated at a semiconductor exhibition that it is building up to 20 wafer fabs, with the overall capacity expansion scale increasing multiple times compared to the past, but it still cannot meet customer demand. The U.S. tariff policy has driven the demand for manufacturing plants in the United States. Axiom has the largest order amount of 440.73 billion yuan, and Chairman Yao ZuXiang pointed out that the cumulative amount of turnkey projects undertaken in Singapore over the past four years has reached 600 billion yuan, with expectations for new projects to follow. HanTang's order amount is approximately 193.937 billion yuan, setting a new record, benefiting from continued plant construction by major clients like Taiwan Semiconductor Manufacturing Company and Micron.FanXuan's order amount reached a new high of 135.1 billion yuan, and Chairman Gao XinMing revealed that order visibility extends at least to 2028, with related projects for clients planned for 2029 and 2030. FanXuan has deployed materials, manpower, and local construction teams to support clients in Taiwan, Arizona in the United States, Japan, and Germany in synchronizing production expansion needs, and is investing in the development of technologies such as CoPoS. ShengHui's order amount exceeds 60 billion yuan, with Taiwan accounting for 68% and semiconductor orders accounting for 63%. In the first half of the year, the after-tax net profit was 2.944 billion yuan, with earnings per share of 23.73 yuan, setting a new high for the same period. Yankee's after-tax net profit in the first half of the year was 2.317 billion yuan, with earnings per share of 17.46 yuan, and the order amount is approximately 51.77 billion yuan, with order visibility reaching the end of 2027.

According to a report by the Economic Daily, with the rising demand for AI and high-performance computing applications, TSMC is expanding its capacity for advanced processes below 3 nanometers at the request of its customers.Industry insiders are optimistic that TSMC's contribution from 3 nanometers in the second half of the year is expected to surpass that of 5 nanometers for the first time, estimating that the single-quarter output value in the third quarter will exceed 400 billion New Taiwan dollars, setting a new record, accounting for more than 30% of revenue, and positively impacting gross margin performance.

On September 2, TSMC Senior Vice President and Co-COO Dr. Wei-Chung Hou stated that the speed of change in AI demand far exceeds past industry experiences. Taking TSMC's equipment demand as an example, the estimated equipment needed for this year at the end of last year was calculated to be 1 times, but just one quarter later it increased to 1.5 times, and by July of this year, it had reached 1.9 times, with demand nearly doubling in just six months.Dr. Hou pointed out that the semiconductor industry has never faced such rapid changes in demand in the past 30 years. The entire industry needs to provide nearly double the original equipment, capacity, and resources in an extremely short time. TSMC is currently constructing 13 fabs in Taiwan and about 5 to 6 overseas, totaling nearly 20 fabs globally, with the scale of construction expanded to about 3 to 4 times that of the past, yet still unable to fully meet customer demand.He emphasized that in the AI era, the entire system or module needs to be optimized, and traditional collaborative models can no longer meet the demand. The supply chain must be restructured into a new cooperation model that is more closely integrated. The entire ecosystem is not yet prepared for such rapid growth, with equipment demand nearly doubling in six months, and almost no suppliers can completely avoid capacity constraints.

According to sources in the materials industry, on September 2, TSMC is expected to continue using traditional micro-bump technology rather than hybrid bonding in the short term for connecting high-bandwidth memory (HBM) with AI accelerators in advanced packaging. Considering the development cycle of related materials, finer pitch micro-bumps are expected to be used until the later stages of HBM4 and the early stages of HBM5. TSMC has requested its materials and equipment partners to develop bonding and underfill solutions for approximately 5-micron bumps, with suppliers from South Korea and Japan beginning development, and mass production of 5μm bumps expected to start in the second half of 2028.Currently, the bump height of the third-generation extended HBM, namely HBM3E, is about 15-25μm, while HBM4 is close to about 10μm. Japanese material suppliers have previously stated that it is difficult to guarantee quality below 15μm. The reduction and refinement of bumps are due to the height limitations of HBM cubes and the demand for higher interconnection density. JEDEC specifies that the maximum height for HBM stacks is 775μm. In TSMC's advanced CoWoS packaging, the HBM stacks assembled by GPU and memory suppliers are mounted onto the silicon interposer via micro-bumps, with the 16-layer DRAM chip stacks completed within HBM packaging by SK hynix and Samsung Electronics.The first and second generations of HBM used larger solder bumps, while micro-bumps became mainstream around the HBM3 generation. SK hynix uses the MR-MUF process, while Samsung Electronics uses TC-NCF. Hybrid bonding allows for thinner and denser interconnections through direct bonding of copper pads; TSMC has utilized this on its SoIC platform for logic chip stacking, but HBM still connects to the interposer using micro-bumps.

According to a report by Juheng.com, after Samsung Electronics took the lead in raising prices for some advanced and mature processes, the market expects TSMC to follow suit, with prices for its various processes likely to increase by 10% to 15% across the board. According to reports from TrendForce and Nomura Securities, TSMC has completed a new round of price negotiations with customers in mid-year, raising prices for the tight supply of some 3-nanometer N3 processes by up to 15% for the second half of the year. The market further anticipates that by early 2027 at the latest, prices for TSMC's advanced processes such as N2, N3, and N5 may increase by another 5% to 10%.TSMC's N2 and N3 capacities have almost been fully booked by Apple and NVIDIA. The prices for mature processes such as N12, N16, and N28, which have not been adjusted for three consecutive years, may also see a simultaneous increase, with a maximum rise of about 10%. According to estimates from Citi Securities, TSMC's capital expenditure will reach $80 billion in 2027, further increasing to $90 billion in 2028, with this year's capital expenditure already raised to between $52 billion and $56 billion. TSMC announced in July that it would expand its investment in the United States to $265 billion. According to Reuters, Samsung raised prices for some new orders of advanced processes in July, with the 4-nanometer SF4 seeing increases of 10% to 15% for customers in China and the United States.

Apple's first 2-nanometer M6 chip officially debuts, equipped with a 12-core CPU, 12-core GPU, and dual 16-core neural network engines, with unified memory bandwidth reaching up to 170GB per second, initially featured in the new Mac mini. This chip is manufactured by TSMC using a 2-nanometer process and is the first to adopt gate-all-around (GAA) nanosheet transistors, making it the world's first consumer-grade 2-nanometer chip.The supply chain is focused on the subsequent high-end M series packaging architecture. Based on the Fusion Architecture of the previous generation M5 Pro, M5 Max, and the four-die design of M5 Ultra, Apple chips have transitioned from a single large die to a modular design. Future M6 Pro, Max, or Ultra are expected to enhance advanced packaging requirements such as SoIC-MH and WMCM, increasing interconnect density with SoIC-MH and integrating logic, LPDDR memory, and high-speed I/O with WMCM.TSMC is actively preparing for expansion, with Zhunan AP6 as the main mass production base for SoIC, Longtan AP3 upgrading to WMCM, and Chiayi AP7 taking on related capacity. Analysts estimate that WMCM's monthly production capacity will reach about 60,000 units by the end of 2026 and over 120,000 units in 2027. Equipment manufacturers such as Hongshuo, Junhua, Yinneng, and material manufacturers Changxing, Xinying Materials, and Yongguang are expected to benefit.

According to the Industrial and Commercial Times, there are widespread rumors in the market that TSMC intends to invest over 30 billion New Taiwan dollars to acquire AUO's two old-generation panel factories, L7 and L5C, located in the Central Taiwan Science Park, adjacent to TSMC's plant, to reserve space for large-size packaging such as CoPoS and FOPLP. Informed sources indicate that TSMC has sent personnel to complete on-site audits, and AUO plans to prioritize the disposal of the two factories, aiming to submit to the board of directors in October, with an estimated completion of production line relocation and factory vacating by the end of the first quarter next year. Both TSMC and AUO have not confirmed this transaction.Semiconductor industry analysts suggest that TSMC is extending from the A14 advanced process and advanced packaging to the COUPE silicon photonics platform, leveraging Taichung's role as a hub for precision optical components to build the Central Taiwan Science Park into a CPO ecosystem. TSMC's existing Fab 15A in the Science Park mainly uses a 28-nanometer process and can support the manufacturing of silicon interposers; the second phase of the Science Park, Fab 25, is planned to build four A14 wafer fabs, with the first two already entering steel structure construction, and the first factory striving for completion before April 2027. The existing advanced packaging and testing facility AP5 in the Science Park has already started CoWoS production, and in the future, it will integrate electronic and photonic chips through the COUPE platform.On the optical side, Largan Precision has recently acquired land and factories in Nantun, Taichung Industrial Zone, and nearby precision machinery clusters, with three transactions totaling approximately 2.568 billion, interpreted by the market as a warm-up for CPO mass production. The company has obtained its first mass production order for fiber optic arrays, with the first automated trial production line aiming for completion by the end of the third quarter, and mass production expected as early as mid-2027, while also laying out micro-lens arrays and integrated FAUs.