hbm

NVIDIA CEO Jensen Huang will meet again with Samsung Electronics Chairman Lee Jae-Yong and SK Group Chairman Chey Tae-Won in New York on September 28 local time, about two months after the three met in San Francisco in July. According to business insiders on the 27th, Lee Jae-Yong and Chey Tae-Won plan to attend the Korean Association's annual dinner at 6 PM that evening in New York, where Jensen Huang will attend as this year's Van Fleet Award recipient. Samsung Electronics is advancing its cooperation with NVIDIA.Topics of interest in the industry include high bandwidth memory. Reports indicate that Samsung Electronics Device Solutions Division Vice Chairman Choi Yong-Hyun met with Jensen Huang during his visit to Korea in June, where they discussed long-term cooperation on next-generation high bandwidth memory such as HBM4E and HBM5. The New York meeting may also involve wafer foundry services and advanced packaging, with discussions on next-generation wafer foundry cooperation also taking place during the June talks.

According to a report by ZDNet Korea on September 28, Samsung Electronics is accelerating the construction of the first mass production line (Ph1) at the Pyeongtaek Fifth Campus (P5) and is discussing with major equipment manufacturers to move the target for Ph1 equipment installation from the originally planned third quarter of next year to the second quarter of next year. P5 is the next-generation semiconductor production base aimed to be operational by 2028, and the construction of the Ph1 cleanroom began in the third quarter of this year.Samsung Electronics had previously advanced the completion of the P5 Ph1 cleanroom, originally scheduled for early next year, by about six months, so the equipment installation is expected around the third quarter of next year. Industry insiders say that the start time for equipment installation is planned to be moved up from July to August next year to around May to June next year; others have indicated that Samsung has even proposed to deliver equipment in the first quarter of next year for temporary storage at other locations, showing a strong willingness to invest early.Discussions on the investment for the second phase of P5 (Ph2) are also progressing. Currently, Ph1 is more likely to be built as a DRAM and HBM production line, while Ph2 is more likely to be built as an advanced NAND production line, including the tenth generation (V10). Equipment industry insiders say that formal purchase orders have not yet been placed, but Samsung has discussed building Ph2 as a NAND production line with partners, and due to the long equipment delivery cycle, they are requesting to prepare relevant components in advance. Reports indicate that large global tech companies are increasing orders for high-performance DRAM and NAND for AI infrastructure, while storage companies like Samsung have limited production capacity. Samsung stated during the second quarter earnings call in July that unmet demand this year will extend into next year, and the supply shortage next year will be more severe than this year, with shortages expected to continue until 2028.

According to a report by ZDNet Korea, Samsung Electronics is adjusting its next-generation DRAM strategy by incorporating the previously project-based B1b into its official roadmap, naming it the first DRAM D0a below 10 nanometers. Previously, D0a referred to vertical transistor DRAM, and this product is now classified separately as D0a-V. This renaming aims to accelerate the introduction of advanced packaging in general DRAM.B1b will manufacture storage cells and peripheral driver circuits on different wafers before bonding them together, using wafer-to-wafer hybrid bonding and directly connecting through copper interconnects. The currently commercialized DRAM is 1c, which is the 6th generation 10 nanometer level, with a line width of about 11 to 12 nanometers; the next generation 1d is the 7th generation 10 nanometer level, with a line width of about 10 to 11 nanometers, considered effectively the last 10 nanometer level product, with the related line width being a marketing term rather than an actual physical size. Vertical transistors can arrange transistors within the cell vertically, reducing the cell area from 6F² to 4F², but they need to address high aspect ratio etching and leakage current, making development more challenging. Wafer-to-wafer hybrid bonding has already been mass-produced in CMOS image sensors and high-stacking NAND.Samsung Electronics is evaluating the use of B1b for the 8th generation high bandwidth memory HBM5. HBM5 is expected to be mass-produced around 2029, aiming to increase operating speed by more than 50% compared to HBM4E. Industry estimates suggest that D0a DRAM based on B1b will be commercially available in about two years, with specific mass production investment schedules likely to be determined by mid-next year.

In episode 166 of the BidClub podcast, chip designer Bubble boi stated that high-bandwidth flash is technically attractive but lacks decisive data center use cases. The information he provided indicated that the main customers he heard about are Chinese clients who find it difficult to obtain or produce high-end HBM.Bubble boi mentioned that HBF and high-end AI flash have a latency of about 5 microseconds, lower bandwidth than HBM, a lower cost per bit, but the total cost may be comparable. He believes the clearest customers are entities unable to obtain HBM, which aligns with the Chinese demand he heard from two to three people, as they cannot adequately manufacture accelerators or are willing to accept non-leading specification products.

According to Money Today on September 21, Samsung Electronics is advancing the expansion of advanced process capacity in wafer foundry due to the growth of the HBM market. To meet the rising demand for HBM4 base chips, it is evaluating the expansion of its 4-nanometer process. Samsung's HBM4 consists of 10-nanometer 6th generation (1c) DRAM core chips and 4-nanometer logic base chips, with the base chips responsible for high-speed data exchange with AI accelerators such as GPUs.Unlike SK Hynix, which uses TSMC's 12-nanometer process for HBM4 base chips, Samsung employs its own 4-nanometer process. This production line is operating at full capacity and has taken on orders from companies like Nvidia and Groq for 3 LPU, and the company has recently raised its prices for new 4-nanometer orders and HBM4 base chips. Samsung expects HBM4 revenue in the third quarter to increase more than threefold quarter-on-quarter, with HBM4 accounting for significantly more than 60% of HBM revenue in the second half of the year. The additional expansion at P4 in Pyeongtaek will mostly be used for 1c DRAM for HBM, with more than half of the wafer foundry's 4-nanometer capacity allocated to HBM4 base chips.HBM4E also uses 4-nanometer base chips, and Samsung provided samples to customers in May. The company is also evaluating the construction of a new 2-nanometer production line for HBM5, aiming for a GAA structure 2-nanometer process and increasing TSV density to improve operating speed by more than 50% compared to HBM4E. Samsung started the first generation of 2-nanometer mass production in the second half of last year and is advancing the second generation of products in the second half of this year. Citigroup expects global HBM bit demand to reach 75.2 billion Gb next year, a year-on-year increase of 62%, with supply around 59.4 billion Gb and a gap of about 21%.

According to a report by Seoul Economic Daily, Samsung Electronics plans to increase the production of the sixth-generation high bandwidth memory HBM4 and the seventh-generation HBM4E, among other HBM4 series, by at least more than double compared to this year. The company intends to outsource the cleaning volume of glass substrates required for thinning HBM DRAM from 20,000 pieces per month this year to 50,000 pieces per month next year, an increase of 2.5 times compared to this year. Last year, the monthly demand for these substrates was about 10,000 pieces, which has already doubled this year compared to last year.The HBM4 and HBM4E that Samsung Electronics is focusing on expanding production are primarily high-stacking products with 12 layers or more. The company began mass production and shipment of HBM4 using sixth-generation 10nm (1c) DRAM and 4nm process-based chips in February this year, and provided 12-layer samples of HBM4E to customers such as Nvidia in May. The industry expects that, based on monthly wafer input, Samsung Electronics' HBM production capacity will increase from about 180,000 pieces this year to about 250,000 pieces next year, an increase of nearly 40%; the shipment proportion of the HBM4 series may rise from about 40% this year to about 80% next year.

Micron Technology will announce its fiscal fourth-quarter results on September 30. NVIDIA CFO Colette Kress stated during the fiscal second-quarter conference call on August 26 that the company is seeing "extreme pricing conditions in memory," with price increases exceeding previous expectations, and that "will further rise next year." Pricing pressure has been reflected in NVIDIA's margins, with Kress guiding that gross margins will bottom out in the fourth quarter in the range of 71%-72%, before recovering to 72%-73% in fiscal year 2028.Kress indicated that the current memory shortage is largely driven by AI infrastructure itself. SK Hynix expects the memory market to reach supply-demand balance no earlier than 2030 and has invested approximately $38.3 billion to expand its two domestic bases in South Korea through 2031. SK Hynix holds about 50% of the high-bandwidth memory market share, leading Samsung's 33% and Micron's 18%.

According to a report by Reuters, informed sources say that South Korea's SK Hynix is in talks with Intel for a deal to produce memory chips in the United States for the first time. One possible option is for SK Hynix to lease part of Intel's long-planned chip manufacturing facility in Ohio; another option is to establish a joint venture with Intel and major cloud service companies eager to secure memory chip supplies.The deal would alleviate pressure on Intel and be a significant victory for the Trump administration. However, sources say that potential opposition from the South Korean side could be a major obstacle, as these technologies are considered sensitive. One source stated that the negotiations are still exploratory, emphasizing that no decisions have been made yet. If an agreement is reached, it is still unclear what type of chips SK Hynix would produce in Ohio.Its product line includes DRAM for servers, PCs, and smartphones, as well as NAND flash memory for long-term storage, and it is also a leading supplier of high bandwidth memory (HBM) used in AI processors.

Citigroup analysts pointed out that leading memory chip manufacturers are expected to benefit from the structural changes in the development of artificial intelligence. The agency anticipates that continuous learning will drive a significant increase in memory demand, leading to a supply shortage in the market that will continue until 2031. Continuous learning strengthens models by training on new tasks and knowledge, which will create a sustained demand for model updates and access to historical data, driving the storage usage of products such as HBM, server DDR5, and eSSD.Citigroup expects HBM bit demand to grow by 62% year-on-year to 75.2 billion gigabits in 2027, and by 69% year-on-year to 127 billion gigabits in 2028. Global DRAM demand is expected to grow by 30% and 35% year-on-year in 2027 and 2028, respectively, while supply is expected to grow by only 19% and 22% during the same period, resulting in supply-demand ratios of -8.7% and -9.7%. In terms of NAND, demand is expected to grow by 29% and 33% year-on-year in 2027 and 2028, respectively, exceeding supply growth of 21% and 25%, with supply-demand ratios of -6.1% and -5.5%.Citigroup's preferred storage targets include Samsung Electronics, SK Hynix, Micron, Sandisk, and Kioxia, corresponding to the logic of storage shortages brought about by continuous learning, demand for HBM and server DDR5, DRAM supply shortages, and tightening supply of high-density eSSD and NAND.

According to the Industrial and Commercial Times, with the expansion of HBM and advanced logic below 2 nanometers, it is estimated that the global silicon wafer supply-demand gap will widen from about 8% by the end of 2026 to 15% in 2027 and 24% in 2028. GlobalWafers, Siltronic, and TSMC are expected to benefit from this. It is noted that mid-2027 will be a critical turning point; if the pace of supply expansion does not keep up, a new wave of shortages and rush buying may occur from the second half of 2027 to the first half of 2028.SEMI statistics show that the global silicon wafer shipment area reached 3.573 billion square inches in the second quarter of 2026, an increase of 9.1% quarter-on-quarter and 7.4% year-on-year. It is estimated that the global monthly production capacity of 12-inch silicon wafers will be about 10.69 million pieces in 2026, an increase of 7% year-on-year, with only about a 3% increase to 11 million pieces in 2027, and an increase of about 6% to 11.7 million to 11.76 million pieces in 2028. The new supply includes about 300,000 pieces from the second phase of GlobalWafers and about 100,000 pieces from Siltronic.It is estimated that the consumption of HBM silicon wafers will increase by 23% and 28% in 2027 and 2028, respectively; new general DRAM production capacity will gradually come online starting in 2027, with an additional monthly capacity of about 350,000 to 450,000 pieces by 2028. In terms of advanced logic, the consumption of logic process silicon wafers is expected to increase by 12% and 11% in 2027 and 2028, respectively. Currently, customer silicon wafer inventory remains at about 100 to 120 days, and it will take time to digest to the normal level of 50 to 70 days.

According to the Chosun Ilbo report on September 15, Samsung Electronics and SK Hynix's third-quarter operating profit consensus has been raised again within three months. Based on reports from major brokerages and overseas investment banks, Samsung Electronics' estimated operating profit for the third quarter is approximately 114 trillion won, an increase of 12.2836 trillion won (12%) from 101.9052 trillion won three months ago, and a 28% increase from 89.4 trillion won in the second quarter. SK Hynix's estimate for the third quarter is 78.8035 trillion won, a 4% increase from 75.7249 trillion won three months ago, and a 30% increase from 60.5426 trillion won in the second quarter.TrendForce expects the fixed transaction prices for general DRAM in the third quarter to rise by 13% to 18% quarter-on-quarter, while NAND flash is expected to rise by 10% to 15%. The securities industry is paying attention to Samsung Electronics' HBM4 revenue share, which expanded from 5% in the first quarter to about 35% in the second quarter, along with improvements in yield rates. SK Hynix maintains the largest market share in HBM, but improvements in Samsung's HBM4 mass production may dilute its supply premium. Citigroup Securities has lowered SK Hynix's third-quarter operating profit estimate from 76.7 trillion won to 74 trillion won due to the strengthening of the won. Micron will announce its fourth-quarter results for fiscal year 2026 (June to August) on the 30th, with revenue guidance of $49 billion to $51 billion.

KB Securities released a report on September 11, indicating that Samsung Electronics' HBM market share is expected to increase from 33% in the second quarter to 40% in the fourth quarter, mainly due to HBM4 sales in the third quarter growing more than three times quarter-on-quarter, and HBM4 is expected to account for over 60% of its total HBM sales in the second half of the year.Samsung Electronics has established comprehensive mass production of HBM4, supplied HBM4E samples to core customers, adopted the HBM5 architecture with 1c core bare chips and 2-nanometer base bare chips, and outlined the roadmap for the next-generation ZHBM. In terms of its foundry business, the 4-nanometer yield has stabilized above 80%, and the 2-nanometer GAA yield has rapidly increased to over 70%. KB Securities analyst Kim Dong-Won stated that the foundry business is expected to turn profitable starting in the third quarter, and the 2-nanometer yield may help it secure orders from major U.S. clients within the year.

According to a Reuters exclusive report on September 10, Chinese AI chip manufacturers have significantly raised prices due to a shortage of high-bandwidth memory. Huawei has raised the indicated price of the Ascend 950DT accelerator card to over 250,000 yuan, an increase of 20% to 50% compared to two months ago. Cambricon has raised the indicated price of its planned 690 chip by 20% to 30%, and both Muxi and Tian Shu Zhi Xin have also implemented similar price increases.The report states that the reasons include U.S. export controls and the high costs of high-bandwidth memory supplies in the gray market. Prices for earlier Huawei products such as the Ascend 950PR and 910C have also increased by about 30%. These price increases have raised the construction costs of AI computing power in China. Huawei, Cambricon, and other companies did not comment.

According to industry news, NVIDIA is considering adjusting the high bandwidth memory solution for the next-generation Rubin Ultra artificial intelligence accelerator from a 12-layer stack to an 8-layer stack.Against the backdrop of rising storage costs, NVIDIA is placing greater emphasis on unit bandwidth costs and overall system economics.

According to the Chosun Ilbo, China's largest DRAM manufacturer Changxin Memory Technologies (CXMT) has launched trial production of the fourth-generation high bandwidth memory HBM3, with initial yield stagnating at 25%, about one-third of the golden mass production yield of 80%. SK Hynix has been mass producing similar products since 2022, with a yield exceeding 90%.The front-end yield of Changxin Memory's HBM3 8-layer stacked products is about 30%, while the back-end yield is approximately 70%, resulting in final good products. The company supplies a small number of samples to Chinese companies such as Alibaba's Pingtouge and Cambricon, and continues to improve yields. Its G4 (17-nanometer) process ordinary DRAM has no major issues, but the DRAM chips used for HBM have larger areas and stricter electrical specifications.The industry attributes the reasons to the insufficient maturity of Through-Silicon Via (TSV) technology. Nomad Semi's analysis shows that Samsung's HBM2 has over 5,000 TSVs per chip, SK Hynix's HBM3 has over 8,000, while Changxin Memory has about 3,000. There is a gap of 4 to 5 years compared to Samsung and SK Hynix.

KB Securities warned that the inventory of memory semiconductors at Samsung Electronics and SK Hynix has fallen to less than 10 days of supply, and the available supply next year will be significantly insufficient. The agency reported on Monday that investment in artificial intelligence infrastructure is expanding at an unprecedented pace, leading to a severe supply shortage in the memory chip market. A key factor is the transition to HBM4, which requires about three times the wafers of traditional DRAM, and limited wafer capacity will reduce the available capacity of traditional DRAM.KB Securities expects that next year, the demand for DRAM and NAND will exceed supply by more than 10 percentage points. Research director Kim Dong-won stated that artificial intelligence servers will consume HBM, server DDR5, and enterprise-grade solid-state drives, potentially leading to a historic shortage. Global hyperscale data center operators have raised their expectations for artificial intelligence infrastructure investment next year to $1.3 trillion, a 60% increase from the previous year. The agency anticipates that memory semiconductors will account for 57% of total investment in artificial intelligence infrastructure next year, up from 14% last year, with TrendForce estimating this ratio could reach as high as 68%. Samsung Electronics' stock price has dropped nearly 28% from its peak, while SK Hynix has fallen nearly 40%.

According to TrendForce's latest research on the memory industry, in the second quarter of 2026, due to a significant increase in the contract price of Conventional DRAM, the overall revenue of the DRAM industry is expected to grow by 59.5% quarter-on-quarter, reaching nearly 154.73 billion USD.With the training of LLM models and AI inference stimulating the demand for AI Servers, shipments of HBM3e, LPDDR5X, and high-capacity RDIMMs are growing simultaneously, while Agentic AI applications are driving the demand for RDIMMs of various capacities. On the supply side, manufacturers' inventories are at a low point, and new supply is prioritized for Server applications, leading to a slight growth in overall DRAM bit shipments in the second quarter.

Samsung Electronics' wafer foundry division has recently surpassed 50% in the allocation of production capacity for the sixth-generation high bandwidth memory HBM4 substrate chips in the 4-nanometer process. The industry states that this division will invest more than half of its 4-nanometer wafers into HBM4 substrate chip manufacturing in the second half of this year to expand supply to companies like NVIDIA, Broadcom, and AMD.Samsung initiated mass production and shipment of HBM4 in February this year and plans to increase supply starting from the third quarter, significantly increasing the related wafer input since mid-year. This chip is based on Samsung's wafer foundry 4-nanometer (SF4) process. As of last month, over 50% of its total 4-nanometer capacity has been allocated to HBM4 substrate chips. According to insiders, Samsung's 4-nanometer process is currently at full capacity, with HBM4 substrate chips accounting for about 50% to 60%, and this high proportion will be maintained in the second half of the year.Samsung's wafer foundry production lines at Pyeongtaek Plant 2 and Plant 3 are mass-producing processes ranging from 4 to 7 nanometers, with a monthly capacity of about 30,000 wafers for the 4-nanometer process. Based on this, the wafer input related to HBM4 substrate chips is estimated to be about 15,000 wafers per month. During the second quarter earnings call, Samsung stated that it expects HBM4 revenue to increase more than threefold quarter-over-quarter in the third quarter, with HBM4 revenue in the second half expected to exceed 60% of the company's overall HBM revenue.

Future Asset Securities analyst Kim Young-gun stated that the expansion of Samsung Electronics' HBM shipments for AI applications is expected to offset the impact of the slowdown in growth of general-purpose memory chips next year. It is anticipated that Samsung Electronics' HBM shipment capacity and average selling price will soar by 57% and 49% respectively by 2027, expected to surpass the projected growth rates of 16% and 20% for general-purpose memory chips.Future Asset expects Samsung's earnings to be weighed down by the strengthening of the Korean won against the US dollar, but overall, it will remain robust. The agency has lowered its operating profit forecast for Samsung in 2026 by 5.7% to 370.057 trillion won and reduced it by 4.2% to 535.682 trillion won for 2027.

Researcher Schulz_Research stated that China's storage advancement is no longer a story of a single company, but rather a division of labor among three companies: CXMT is responsible for DRAM wafers, YMTC is responsible for NAND and has added DRAM in its latest factory, and the foundry controlled by YMTC, XMC, is responsible for stacking products from both. This division corresponds to the rules set by Beijing since late December last year, which state that new factory approvals must show that at least half of the equipment is domestically sourced, with exemptions only granted when there are no domestic options available. YMTC's Wuhan Phase III is the first advanced storage project to pass this rule and is set to begin production later this year.CXMT operates three 300mm DRAM factories, each producing about 100,000 wafers per month; models indicate it will reach 350,000 wafers by the end of 2026, and if all announced projects are completed, the total will exceed 600,000 wafers. YMTC's first two factories in Wuhan have a combined capacity of 200,000 wafers, with Phase III expected to reach 50,000 wafers by 2027 and full production of 100,000 wafers, along with plans to build two more factories of similar scale. XMC has two 12-inch factories, each with about 30,000 wafers, and an HBM packaging line producing about 3,000 wafers per month. China supplies about 10% of the global DRAM bits, with YMTC accounting for 14% of NAND bit shipments in the second quarter, and China consumes about 30% of global storage.CXMT has begun mass production of DDR5 and LPDDR5 and plans to start mass production of HBM3 this year, having already sent samples to domestic AI hardware developers. XMC has spent two years building HBM packaging based on hybrid bonding and YMTC's stacking IP, and is still advancing TSV technology.