Samsung Electronics advances the expansion of the P5 factory in Pyeongtaek into a three-story wafer plant
According to the Dong-A Ilbo, Samsung Electronics plans to expand the core project of the P5 1·2 factory (Fab 5·6) in Pyeongtaek, Gyeonggi Province, from a dual-layer wafer factory to a three-layer wafer factory to respond to the global artificial intelligence semiconductor and memory supercycle and maximize production capacity. Samsung Electronics has recently submitted a plan to change the industrial park, proposing to increase the floor area ratio from 350% to a maximum of 490%. This change must be reviewed by the Gyeonggi Province governor and approved by the Ministry of Land, Infrastructure and Transport's industrial site policy review committee before it can be finalized.The Pyeongtaek P5 1·2 factory is the largest semiconductor factory in the world under a single standard, which began construction in 2022 and aims to be completed by 2030. It will produce high bandwidth memory (HBM), high-end DRAM, next-generation V-NAND, and advanced foundry products. The currently operational Pyeongtaek P4 uses a dual-layer structure with four clean rooms in a single building; if the change is approved, P5 will be configured with up to six clean rooms, and the number of clean rooms and production capacity is expected to increase by about 1.5 times. SK Hynix also plans to use a three-layer structure for all newly constructed wafer factories in the Yongin semiconductor cluster.Market research firm Counterpoint Research expects the global memory market size to increase from approximately 360 trillion won last year to 1,500 trillion won this year and 2,100 trillion won next year. In the context of increasingly difficult access to electricity, water, and land, increasing the floor area ratio to build three-layer wafer factories has become an important path to overcome the physical limitations of limited space and rely on the existing semiconductor industry ecosystem.
