TSMC accelerates its layout in CPO, and the industry is optimistic about forming a new Moore's Law

According to Taiwan's "Commercial Times" report on September 14, as the computing power of GPUs and ASICs continues to rise, traditional copper interconnects are gradually approaching the limits of power consumption and signal transmission. TSMC is accelerating its layout for co-packaged optics (CPO). The industry is optimistic that if CPO bandwidth continues to double every two years, it may form the "CPO Moore's Law" of the AI era. Industry analysis indicates that the upgrade of CPO bandwidth mainly has three paths: including increasing single-channel speed from 200G to over 400G, expanding the number of optical channels from 16 to 32, 64 or more, and introducing wavelength division multiplexing (WDM). By 2040, the theoretical value could reach about 128 times the current level, with long-term potential for development towards hundreds of T based on the current level of about 3.2T.

TSMC's role in optical interconnects has extended from wafer foundry to system integration, gradually integrating computing, HBM memory, and high-speed I/O from 3DFabric, CoWoS, SoIC to silicon photonics and CPO. When high-speed electrical signals exceed 200G, signal attenuation increases after passing through longer copper paths such as ABF substrates, PCBs, and connectors, leading the industry to develop shorter copper paths and longer optical paths. In terms of packaging architecture, the optical engine is currently laid out on the substrate, and the next step is expected to place CPO in the intermediary layer, with future possibilities of using SoIC technology to achieve 3D vertical integration of photonic integrated circuits (PIC) and ASICs. Industry players indicate that CPO still needs to overcome challenges in packaging, optical coupling, and testing before mass production can be achieved.