AMD reveals its 2-nanometer server processor layout, aiming for mass production in 2027

AMD disclosed server processor and die interconnect layout at the In Depth technology forum. Venice uses TSMC's N2 process and CoWoS-L advanced packaging, and introduces elevated fan-out bridge (EFB). The subsequent Verano will adopt the N2P process. AMD's server architecture head Mahesh Subramony stated that as the number of computing cores increases, more data needs to be transmitted between dies, and EFB reduces power consumption and latency through short-distance interconnects. AMD expects the data center CPU market size to grow from approximately $26 billion in 2025 to about $220 billion in 2030, with a compound annual growth rate of over 50%.

In terms of packaging collaboration, ASE and SPIL are involved in the development and validation of wafer-level 2.5D bridge interconnects, and AMD has completed panel-level EFB interconnect validation with Powertech. AMD announced in May 2026 that it will invest over $10 billion in the Taiwanese industrial ecosystem to expand strategic cooperation and advanced packaging capabilities. Regarding product progress, the Venice SP7 platform has been shipped, with the SP8 aimed at the enterprise market expected to be supplied in the first half of 2027, and Verano and Venice-X scheduled for release in the second half of the same year, with related server processor products targeted for mass production in 2027.