Huawei Kirin 9050 series NPU performance improved by 140%

The Huawei Kirin 9050 series chips are equipped with a new generation Da Vinci architecture NPU, supporting 30B large models to run on the device side without the need for internet connection or cloud invocation. This NPU has a performance improvement of 140% and a power consumption reduction of 66%, supporting the Transformer engine, ultra-low power perception engine, and CANN heterogeneous computing architecture.

The Kirin 9050 series is the first τ chip to adopt "logical folding" technology, with its NPU supporting the industry's first 30B MoE large model on-device, and supporting multi-level storage-computation collaborative optimization and low-bit quantization. Related features include AI screen reading, Xmage Smart Capture 2.0, AI eye movement page turning, and screen-off map 2.0. Xu Songyu, the head of Huawei's semiconductor business wireless terminal chip product management department, previously stated that Huawei aims to achieve a P core frequency breakthrough of 5GHz by 2031.